Method for evaluating wafer configuration, wafer, and wafer sorting method

ABSTRACT

A method for evaluating a wafer configuration includes: obtaining plural wafer configuration profiles from a central wafer portion to an edge portion along the entire periphery at a prescribed angular space; providing a first region for calculating a reference line for each profile in the central side of the wafer; calculating the reference line in the first region; providing a second region in the peripheral side of the wafer outside the first region; extrapolating the reference line calculated in the first region to the second region; analyzing a value obtained by subtracting the reference line value in the second region from an actually measured value in the second region; calculating the maximum value among the values as a surface characteristic and the minimum value among the values as a surface characteristic; and, evaluating configuration uniformity in the peripheral portion of the wafer from plural surface characteristics and surface characteristics.

TECHNICAL FIELD

The present invention relates to a method for evaluating a configurationof a wafer represented by a silicon wafer, a wafer suitable for anexposure system and a sorting method for a good quality wafer.

BACKGROUND ART

Recently, an integration level in a semiconductor device has beenbecoming increasingly higher because of the remarkable progress in thesemiconductor device technology, and with this progress, a demand forquality of a silicon wafer or the like has also been becoming moresevere. As one of the important characteristics required to the siliconwafer as described above, there is an issue about surfaceconfigurations. This is because a higher integration level of asemiconductor device has brought about miniaturization of a device size,and for instance, slight undulation or the like on a silicon wafer maylead to faults in a device pattern during the photolithography step orother steps. In addition, in order to effectively use a wafer, there isrequired a wafer which has excellent high flatness up to the utmostouter peripheral portion (the very limit of the chamfered portion) ofits main surface.

There have been conventionally used site flatness based on the frontside reference, SFQR (Site Front Least Square Range) and others as theindex for evaluating flatness of the wafer mentioned above. SFQR is asum of absolute values of the respective maximum displacements in theplus side and minus side from the reference plane which is a flat planein a site obtained by calculating data with the method of least squares,which is evaluated for each site. A size of the site is generally 20 mmsquare or 25 mm square.

DISCLOSURE OF THE INVENTION

Improvements have also been realized on precision, etc. of an exposuresystem along with the progress of the high integration level asdescribed above, while troubles have frequently occurred that theexposure system stops in the course of patterning on a wafer.

These troubles have been considered caused by a factor of the exposuresystem, and an influence of a fine configuration of a wafer used in theexposure system as well. However, the wafer is of a level which becomesno issue when evaluated with an index such as SFQR; therefore, a clearcause for the troubles has been unknown. Consequently, there has arisena necessity for evaluating a wafer configuration using a factor otherthan SFQR to supply a wafer not causing the troubles in the exposuresystem.

When evaluated with SFQR or the like as described above, in particular,flatness in an inner side portion of the wafer is evaluated with goodprecision, whereas there is a case where exact evaluation is not alwaysassured in a peripheral portion of the wafer, especially in the vicinityof a boundary between a chamfer portion and a main surface of the wafer.

With the foregoing difficulties of the prior art in view, it is anobject of the present invention to provide a method for evaluating aconfiguration of a wafer from a different viewpoint from theconventional SFQR or the like, a wafer with less troubles in an exposuresystem or the like, and a sorting method for a good quality wafer.

In order to achieve the above object, a method for evaluating a waferconfiguration of the present invention comprises the following steps of:obtaining plural wafer configuration profiles of from the centralportion of a wafer to the edge portion thereof along the entireperiphery thereof at a prescribed angular space; providing a firstregion for calculating a reference line for each of the profiles in thecentral side of the wafer; calculating the reference line in the firstregion; further providing a second region in the peripheral side of thewafer outside the first region; extrapolating the reference linecalculated in the first region to the second region; analyzing a value(an actually measured value−a reference value) obtained by subtractingthe reference line (the reference value) in the second region from aconfiguration (the actually measured value) in the second region;calculating the maximum value among the values as a surfacecharacteristic A and the minimum value among the values as a surfacecharacteristic B; and evaluating configuration uniformity in theperipheral portion of the wafer from plural surface characteristics Aand surface characteristics B obtained along the entire peripheralportion of the wafer.

In the conventional SFQR or the like, a wafer surface is divided intoareas (sites) each about 20 mm square or about 25 mm square in which areference plane is prepared for evaluation, but in this case, since areference plane is prepared in a narrow area, the SFQR was averagedwithin the plane; it is often impossible to perform exact evaluation ondeterioration of an actual configuration or the like. Especially, inthis conventional evaluating method, a configuration of the peripheralportion of the wafer cannot be evaluated accurately.

A surface characteristic A (hereinafter also referred to as A parameter)and a surface characteristic B (hereinafter also referred to as Bparameter) obtained by the method for evaluating a wafer configurationaccording to the present invention can preferably perform very exactevaluation of a surface configuration in the peripheral portion of thewafer. Especially, by analyzing plural surface characteristics A andsurface characteristics B obtained along the peripheral portion of thewafer as performed in the present invention, configuration uniformity inthe peripheral portion of the wafer can be evaluated. At this time, itis preferable to evaluate the configuration uniformity in the peripheralportion of the wafer from a difference between the maximum value and theminimum value of the plural surface characteristics A obtained in theperipheral portion of the wafer (this configuration uniformity in theperipheral portion is referred to as A parameter peripheral portionuniformity).

Furthermore, at this time, it is preferable to evaluate theconfiguration uniformity in the peripheral portion of the wafer from adifference between the maximum value and the minimum value of the pluralsurface characteristics B obtained in the peripheral portion of thewafer (this configuration uniformity in the peripheral portion isreferred to as B parameter peripheral portion uniformity).

More preferably, a difference between the surface characteristic A andthe surface characteristic B (a surface characteristic (A−B)) isobtained from each of the profiles in advance, and the configurationuniformity in the peripheral portion of the wafer is evaluated from adifference between the maximum value and the minimum value of the pluralsurface characteristics (A−B) obtained in the wafer surface (thisconfiguration uniformity in the peripheral portion of the wafer ishereinafter referred to as (A−B) parameter peripheral portionuniformity). Moreover, the configuration uniformity in the peripheralportion of the wafer may be evaluated with standard deviations of pluralsurface characteristics A, surface characteristics B or differencestherebetween (surface characteristics (A−B)) obtained in the peripheralportion of the wafer as variations.

Here, the wafer configuration measured with a prescribed space withinthe wafer surface is displacement (height or roughness) in the directionvertical to the wafer surface or a wafer thickness. Evaluation on thedisplacement in the direction vertical to the wafer surface makes itpossible to perform evaluation based on the front side reference.Further, evaluation on the wafer thickness makes it possible to performevaluation based on the back side reference.

The prescribed space described above is preferably 1 mm or less (but inexcess of 0 mm).

The prescribed angular space to obtain wafer configuration profiles ispreferably 1 degree or less (but in excess of 0 degree).

Especially, an index for the configuration uniformity in the peripheralportion of the wafer can be obtained by attaining plural surfacecharacteristics A and surface characteristics B along the entireperiphery (along the peripheral portion of the wafer).

Further detailed description will be given of the method for evaluatinga wafer configuration of the surface characteristics A and surfacecharacteristics B. In the method according to the present invention, asshown in FIG. 1, a reference line is prepared in a global (extensive)region (a first region) for calculating a reference line from a waferconfiguration (each of profiles), and the reference line is used bybeing extrapolated to a region (a second region) to be evaluated such asthe peripheral portion of the wafer for analyzing the surfacecharacteristics of the second region, the surface characteristics of theregion being evaluated. Measuring a value obtained by subtracting thereference line from the actual configuration (an actually measuredvalue−a reference value), the calculated maximum value is evaluated as arise (A in FIG. 1) and the calculated minimum value as a sag (B in FIG.1).

In other words, in the method according to the present invention,without the use of the conventional SFQR or the like wherein evaluationis performed on each site, a reference line is prepared in an extensivespecified region (a first region) on a wafer surface, which is an arealarger than the site size to be evaluated by the SFQR or the like; thesurface characteristics in a region to be evaluated (a second region)other than the first region is evaluated based on the reference lineprepared in the extensive specified region (the first region).

A wafer most suitable for an exposure system can be defined byperforming the method for evaluating a wafer configuration of thepresent invention. A yield in the exposure system (such as amisalignment occurrence frequency in a device pattern) is mainly due tothe surface characteristic A. In a preferable wafer, an average value ofits surface characteristics A is smaller than 150 nm. As for an abnormalstop or the like of the system, it became clear that frequent abnormalstops or the like occur in a case where there is locally present a largechange in values of the surface characteristic B obtained by evaluatingthe peripheral portion of the wafer according to the method forevaluating a wafer configuration of the present invention. To beconcrete, frequent abnormal stops occurred in a case where a differenceof the maximum value and the minimum value of plural surfacecharacteristics B obtained within the wafer surface (the B parameterperipheral portion uniformity) is larger than 600 nm. Therefore, a wafermost suitable for the exposure system has the difference of 600 nm orless.

Moreover, when evaluation is performed with a difference between asurface characteristic A and a surface characteristic B, that is asurface characteristic (A−B), wafers to be used in the exposure systemcan be precisely sorted into good wafers and poor wafers. That is tosay, a wafer suitable for the exposure system has the difference betweenthe maximum value and the minimum value of plural surfacecharacteristics (A−B) obtained within the wafer surface (the (A−B)parameter peripheral portion uniformity) of preferably 500 nm or lessand more preferably 400 nm or less.

Note that those values of the above surface characteristics A and B areevaluated by using data with a boundary (an arbitrary position X)between the first region and the second region at a position having adistance of 30 mm from the peripheral portion of the wafer excluding 1mm of the peripheral portion of the wafer (excepting a chamfer portion).

The wafer described above has not extreme sags and local sags in theperipheral portion of the wafer when evaluated with the surfacecharacteristics A and B.

While there are conceivably a variety of wafer manufacturing processesfor manufacturing the above wafer, for example, where a wire saw is usedin a slicing step, slicing is performed such that no abnormal cutting-inby a wire occurs in the peripheral portion of the wafer. In an etchingstep, a contact area of a wafer with an etching drum for supporting thewafer is minimized. In a case including a surface grinding step, nogrinding striation is generated. Sags in the peripheral portion of thewafer due to lapping are prevented from generating. There are availablea process for manufacturing a wafer under controlling a polishingpressure on the peripheral portion of the wafer in a polishing step andother steps. As described above, various improvements can be attained insteps of a wafer manufacturing process, and hence no specific limitationis imposed on the manufacturing process for the wafer.

Even when a wafer is manufactured by means of various methods asdescribed above, it is difficult to perfectly manufacture wafers fallingwithin the range above described; therefore there are sorted wafers eachhaving a difference between the maximum value and the minimum value ofthe plural surface characteristics B (the B parameter peripheral portionuniformity) of 600 nm or less obtained by the use of the method forevaluating a wafer configuration, the sorted wafers being preferablyused in an exposure system.

Furthermore, there are preferably sorted wafers each having a differencebetween the maximum value and the minimum value of the obtained pluralsurface characteristics (A−B) (the (A−B) parameter peripheral portionuniformity) of 500 nm or less, the sorted wafers being used in anexposure system. More preferably, there are sorted wafers each having adifference between the maximum value and the minimum value of theobtained plural surface characteristics (A−B) (the (A−B) parameterperipheral portion uniformity) of 400 nm or less, the sorted wafersbeing used in an exposure system.

Thus, by the use of the method for evaluating a wafer configuration ofthe present invention, wafers are sorted and the sorted wafers are usedin an exposure system; abnormal stops or the like of the exposure systemmay be remarkably reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an explanatory view showing schematically three-dimensionalrelations between a reference line and a first region and a secondregion in the method for evaluating a wafer configuration according tothe present invention;

FIG. 2 is an explanatory view showing a first region and a second regionin the method for evaluating a wafer configuration according to thepresent invention;

FIG. 3 is an explanatory view showing an example of a region forevaluation in the method for evaluating a wafer configuration accordingto the present invention;

FIG. 4 is a graph showing relations between a measurement point in aperipheral portion of a wafer S1 and each of A and B parameter values inExample 1;

FIG. 5 is a graph showing relations between a measurement point in aperipheral portion of a wafer S2 and each of A and B parameter values inExample 2;

FIG. 6 is a graph showing relations between a measurement point in aperipheral portion of a wafer S3 and each of A and B parameter values inExample 2;

FIG. 7 is a graph showing relations between a measurement point in aperipheral portion of a wafer S4 and each of A and B parameter values inExample 2;

FIG. 8 is a graph showing relations between a measurement point in aperipheral portion of a wafer S5 and each of A and B parameter values inComparative Example 1;

FIG. 9 is a graph showing B parameter peripheral portion uniformity ineach of the wafers S1 to S5;

FIG. 10 is a graph showing (A−B) parameter peripheral portion uniformityin each of the wafers S1 to S5;

FIG. 11 is a schematic side view showing an essential structure of afirst embodiment of an apparatus for evaluating a wafer configurationaccording to the present invention; and

FIG. 12 is a schematic side view showing an essential structure of asecond embodiment of an apparatus for evaluating a wafer configurationaccording to the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the method for evaluating a wafer configuration accordingto the present invention are described in detail below with reference tothe accompanying drawings.

FIG. 2 shows schematically a configuration of a wafer W. Generally, aperipheral edge portion of the wafer W is chamfered to prevent crackingor the like, a chamfered portion Wm being formed. Usually, thischamfered portion Wm is ignored in evaluating a wafer configuration, andout of an object of measurement.

Evaluating a wafer configuration (a wafer profile) is often performed ona region of a main surface Wn of the wafer W which is formed byexcluding an area with the width of about 3 mm or about 2 mm from thechamfered portion Wm of the wafer W. However, recently it is required toevaluate the region which is formed by excluding an area with the widthof 1 mm from the chamfered portion or the region to the very limit ofthe boundary between the main surface and the chamfered portion.Therefore, while there is no limitation on the evaluation region(especially, the excluding area), considering measuring precision andthe analyzed data precision, in the present state it is preferable toevaluate the region formed by excluding an area with the width of about1 mm.

FIG. 1 schematically shows displacement in thickness of a surface of thewafer W. A main purpose of the method for evaluating a waferconfiguration according to the present invention is to quantify rises orsags which are easily generated on an area with the width of about 10 mmof the peripheral portion of the wafer (10 mm from the chamfered portionWm).

In the method for evaluating a wafer configuration according to thepresent invention, as shown in FIG. 1, a reference line 10 is preparedwithin an extensive region (a first region) W1 for calculating thereference line in a wafer surface from the basic configuration of thewafer W; the reference line 10 is extrapolated to a region (a secondregion) W2 to be evaluated on the peripheral portion of the wafer, andis used thereon for analyzing the surface characteristics of the secondregion W2 for analyzing the surface characteristics of the region W2.

A value (an actually measured value−a reference value) obtained bysubtracting the reference line 10 (a reference value) from an actualconfiguration (an actually measured value) of the wafer is measured, andthe measured maximum value is evaluated as rises A, the measured minimumvalue being evaluated as sags B. It is to be noted that, in FIG. 1,designated by Wc is a central portion of a wafer, We is an edge portionof the wafer, and X is a boundary between the first region W1 and thesecond region W2, which is provided at an arbitrary position.

In the method for evaluating a wafer configuration by preparing areference line, a configuration of a wafer is measured with a prescribedspace on a surface of the wafer; the measured wafer configuration issuccessively stored; a configuration profile of from the central portionWc of the wafer W to the edge portion We thereof as shown in FIG. 3 isobtained from the stored configuration; there is calculated a referenceline up to a boundary X of the first region W1 provided at an arbitraryposition away from the central portion (in the radial direction of thewafer); and then a difference between a configuration (an actuallymeasured value) at an arbitrary position (in the direction of the waferthickness) and a value (a reference value)of the reference line 10 atthis position is analyzed to be calculated as the surfacecharacteristics.

The prescribed measurement space on the wafer surface should bepreferably within 1 mm. The space is naturally more than 0 mm, but byperforming evaluation with the smallest possible space, more accurateconfiguration can be quantified.

The reference line may be approximated by a straight line or a curvedline most well reflecting a configuration of the central portion of thewafer W, but usually the central portion of the wafer W is polished to ahigh flatness level, so that the reference line is fully approximated bythe straight line.

Here, an arbitrary position X of a boundary between the first region W1and the second region W2 is preferably provided at an arbitrary positionin the radial direction of the wafer W and in an area (an area where thefirst region is as extensive as possible) of the wafer W where noperipheral sag nor rise is generated. For instance, usually sags and thelike occur in the area outside of about 10 mm away from the peripheraledge of the wafer, so that the arbitrary position (boundary) X shouldpreferably be provided at a position of about 30 mm away from theperipheral edge of the wafer. It is preferable to prepare a referenceline or a reference plane at a position of 70 mm away from the centralportion of the wafer in the case of an 8 inch wafer (200 mm in diameter)and at a position of 120 mm away from the central portion in the case ofa 12 inch wafer (300 mm in diameter). However, this position may befreely changed so that the wafer quality can be evaluated mostaccurately.

In the method of calculating the specific surface characteristics to beevaluated by preparing a reference line, a configuration profile of awafer W of from the central portion Wc to the edge portion We isobtained; a reference line of from the central portion Wc to anarbitrary position X is calculated; then there is analyzed a valueobtained by subtracting a reference line at an arbitrary position in therange of from the arbitrary position X to the edge portion We from aconfiguration at this position [a configuration at an arbitrary position(an actually measured value)−a reference line at an arbitrary position(a reference value)]; and the maximum value among the analyzed values(usually the positive maximum displacement amount or the maximumthickness difference) is calculated as the surface characteristic A(rises). This surface characteristic A quantitatively indicates a risingconfiguration on the peripheral portion of the wafer.

Also, a configuration profile of from the central portion Wc of thewafer W to the edge portion We is obtained; a reference line of from thecentral portion to an arbitrary position X is calculated; then there isanalyzed a value obtained by subtracting a reference line at anarbitrary position in the range of from the arbitrary position X to theedge portion We from a configuration at this position [a configurationat an arbitrary position (an actually measured value)−a reference lineat an arbitrary position (a reference value)]; and the minimum valueamong the analyzed values (usually the negative maximum value) iscalculated as the surface characteristic B (sags). This surfacecharacteristic B quantitatively indicates a sagging configuration on theperipheral portion of the wafer.

In the present invention, in order to evaluate the whole wafer,providing a plurality of radial measuring positions as indicated by thedotted line in FIG. 3, configuration profiles of from the wafer centralportion Wc to the edge portion We (excluding the chamfer portion Wm) areobtained for each given angular space (θ), and such a one-dimensionalanalysis is performed for each of the configuration profiles, therebythe surface characteristics A and B being obtained.

As a result, plural surface characteristics A and B are obtained alongthe wafer peripheral portion. It is especially preferable to analyze aconfiguration profile radially along about 400 lines (at an angularspace of about 1 degree or less) within the wafer surface. While thevalue of the angular space is naturally in excess of 0 degree, veryexact evaluation can be performed in the wafer peripheral portion withthe angular space of 1 degree or less. Note that it is preferable toperform evaluation excluding parts including a notch, an orientationflat and a letter printed with a laser mark because the parts causeabnormal data easily.

More exact evaluation can be performed than in a conventional waferconfiguration evaluation by using surface characteristics A and B. Inaddition, evaluation can be performed on configuration uniformity in thewafer peripheral portion by analyzing surface characteristics A and Balong the wafer peripheral portion..

Next, an evaluating apparatus for performing the above evaluation isdescribed below. FIG. 11 is a schematic explanatory view showing anessential structure of the apparatus for evaluating wafer configurationaccording to the present invention. An apparatus 20 for evaluating awafer configuration shown in FIG. 11 is an apparatus used formeasurement and analysis of displacement of a surface of a wafer W,which comprises a test stand 22, and a displacement measuring unit 26having a displacement gauge 24 equipped with a laser oscillator or anautomatic focusing mechanism, a computer 28, etc., and opticallymeasures shifts in the distance from the previously calibrated referencepoint as the displacement. In the embodiment shown in FIG. 11, thedisplacement measuring unit 26 functions as a configuration measuringunit.

The test stand 22 is a stand used for placing thereon a silicon wafer Was an object to be measured. The displacement gauge 24 is an apparatusfor irradiating a laser beam with a prescribed space onto a surface of asilicon wafer W placed on the test stand 22, and for instance, a HeNelaser or the like is used as the laser beam. The displacement gauge 24is equipped with an automatic focusing mechanism (not shown), and thisautomatic focusing mechanism is provided with, for instance, a CCD(Charge Coupled Device) camera (not shown), an automatic focusingcircuit (not shown), and others, and can automatically focus on an imagereflected from the silicon wafer of the laser beam which is emitted fromthe laser oscillator.

The displacement gauge 24 measures the displacement from a referencepoint when focused by the automatic focusing mechanism, and inputs thedisplacement data into the computer 28.

The computer 28 is equipped with a CPU (Central Processing Unit), an RAM(Random Access Memory), an ROM (Read Only Memory), etc. The computer 28into which the displacement data output from the displacement gauge 24are input, reads the analysis program stored in the ROM using the RAM asa work area, and calculates the surface characteristics A and B of thewafer quality according to the present invention from the inputdisplacement data with the CPU. The surface characteristics areparameters especially used for evaluation of a peripheral portion of thewafer.

In other words, the computer 28 comprises a storage means forsuccessively inputting and storing configuration data obtained by thedisplacement measuring unit (the configuration measuring unit) 26, and asurface characteristic calculating unit for reading a configuration data(an actually measured value) of from the central portion of the wafer Wto the edge portion thereof from the storage device, calculating areference line (a reference value) from the central portion of the waferto an arbitrary portion, then analyzing a value (an actually measuredvalue−a reference value) obtained by subtracting the reference line orthe reference plane from an arbitrary position, and calculating theanalyzed difference as the surface characteristics.

FIG. 12 is a schematic explanatory view showing an essential structureof another embodiment of the apparatus for evaluating a waferconfiguration according to the present invention. In another embodimentfor the apparatus for evaluating a wafer configuration, a thickness maybe measured with a flatness measuring unit based on an electrostaticcapacitance system in place of displacement of the wafer surface. Theflatness measuring unit based on the electrostatic capacitance system isused as a thickness measurement unit 34 equipped with a thickness gauge32 comprising electrostatic capacitance type of upper and lower sensors32 a, 32 b arranged such that the wafer W is held between them as shownin FIG. 12, and measures the thickness of the wafer W by measuring thedistances between the sensors 32 a, 32 b and upper and lower surfaces ofthe wafer W, respectively. As the flatness measuring unit based on theelectrostatic capacitance system, a commercial non-contact type of waferthickness, flatness and BOW/WARP measuring unit such as Ultra Gauge 9900produced by ADE Corp. may be used.

The apparatus 30 for evaluating a wafer configuration shown in FIG. 12comprises a wafer holding jig 36 for holding a wafer W, the abovementioned thickness measuring unit 34, and a computer 28, and is usedfor measuring a thickness of the wafer W. In the embodiment shown inFIG. 12, the thickness measuring unit 34 functions as a configurationmeasuring unit.

Thus, any type of evaluating apparatus may be used without any specificlimitation, provided that it can finely and accurately evaluateconfigurations (irregularities) of the wafer W.

The surface characteristics A and B are evaluated on the basis of thedisplacement or thickness measured as described above. Specifically, thereference line is a line calculated by means of the method of leastsquares and other methods. Therefore, as to the space with which dataare to be sampled, the finer, the better. Specifically, a proper rangefor the space should be 1 mm or less.

Next, the configuration evaluation using the surface characteristics Aand B actually calculated by the apparatus for evaluating a waferconfiguration according to the present invention is described below.FIG. 1 is a view showing values for the surface characteristics A and Bof a prescribed wafer, and a configuration profile on a cross sectionthereof. In an analysis program of the surface characteristicscalculating means, an equation for calculating the surfacecharacteristics A and B is programmed for each profile. Furthermore, theanalysis program is a software evaluating an average value, a standarddeviation, a maximum value and a minimum value of plural surfacecharacteristics A, B or (A−B) obtained from profiles along a peripheralportion of the wafer.

In the analysis program, as for the surface characteristic A, thicknessdata of a mirror polished silicon wafer are read with an arbitrary space(about 1 mm) on the silicon wafer from the central portion thereoftoward the edge portion; then a reference line is prepared using thethickness data in an extensive first region by means of the method ofleast squares; a difference between the reference line and aconfiguration in a second region to be evaluated is calculated, and themaximum value within the area is analyzed.

As for the surface characteristic B, thickness data of a mirror polishedsilicon wafer are read with an arbitrary space (about 1 mm) on thesilicon wafer from the central portion thereof toward the edge portion;then a reference line is prepared using the thickness data in anextensive first region by means of the method of least squares; a valueobtained by subtracting the reference line from a configuration in asecond region to be evaluated is calculated, and the minimum valuewithin the area is analyzed.

The analysis described above is conducted on each profile along theperipheral portion of the wafer. By analyzing surface characteristics Aand B obtained from the plural profiles, uniformity (variation) of aconfiguration in the peripheral portion of the wafer is evaluated. To beconcrete, evaluation is performed on an average value, a standarddeviation, a maximum value, a minimum value and others of surfacecharacteristics A and B or a difference between the surfacecharacteristic A and the surface characteristic B (hereinafter may bereferred to as a surface characteristic (A−B) or (A−B) parameter).

With the apparatus for evaluating a wafer configuration according to thepresent invention described above, by reading into a computer andanalyzing displacement data measured using a laser beam, or thicknessdata measured with an electrostatic capacitive type thickness measuringinstrument, there can be calculated surface characteristics A and B,configuration uniformity in the peripheral portion and others.

As described above, according to the present invention, a surfaceconfiguration of a wafer, especially a peripheral portion thereof can beevaluated accurately on the basis of a specific standard from adifferent viewpoint from the conventional techniques such as SFQR. Inaddition, by obtaining and analyzing plural surface characteristics A orB along the peripheral portion of the wafer, evaluation on configurationuniformity of the wafer peripheral portion can be realized. It ispossible to obtain more effective information as compared to theconventional evaluation for the wafer configuration, and hence problemsin a device fabricating process such as a process using an exposuresystem and others can be solved. Moreover, the surface characteristicscan be fully used as parameters for analysis of various experimentaldata, too.

EXAMPLES

The present invention will be further described more detailedly by wayof the following examples which should be construed illustrative ratherthan restrictive.

Example 1

Description will be given of an example of the configuration evaluationmethod of the present invention. In this example, evaluation wasconducted on an 8-inch mirror-polished wafer (200 mm in diameter and 0.5mm in width of a peripheral edge portion being a chamfered portion)manufactured in a common manufacturing process. The wafer is referred toas S1.

In the configuration evaluation, the wafer thickness was measured atpositions with a space of 0.95 mm on the whole surface of the wafer(excluding the chamfered portion of an area with 0.5 mm in width of theperipheral portion); the measured wafer thickness data were successivelystored; configuration profiles of the wafer of from the central portionto the edge portion (98.5 mm away from the central portion) as shown inFIG. 1 were read from the stored wafer thickness data; a reference linewas calculated using the values from the central portion (in thedirection of the wafer diameter) to an arbitrary position X (70 mm awayfrom the central portion and 30 mm away from the edge portion) by themethod of least squares; then the difference between the thickness atthe arbitrary position and the value of the reference line (a virtualthickness) at the same position was analyzed; and the analyzeddifference was calculated as the surface characteristics. In otherwords, the surface characteristics A and B are the maximum value andminimum value in the second region to be evaluated of 70 mm to 98.5 mm,respectively

These values were analyzed using plural profiles from the center portionof the wafer to the edge portion thereof in radial directions. Actually,an analysis was performed on 400 profiles obtained at a prescribedangular space(θ).

Then, there ware analyzed the surface characteristics A and B obtainedfrom the profiles. While the surface characteristics A and B have 400values, evaluation thereof was performed excluding 13 values thereofwhich were obtained from profiles intersecting a notch.

In FIG. 4, there are shown changes in A and B parameter values atevaluation positions for the evaluated surface characteristics. Theabscissa of FIG. 4 indicates the evaluated position θ. The position θ isobtained by plotting values evaluated rotating the wafer in the range of360 degrees in the clockwise direction at the notch as 0 degrees. Theordinate indicates the A and B parameter values in μm unit.

With such forms as shown in FIG. 4, there can be confirmed uniformity inthe peripheral portion of the wafer based on the surface characteristicsA and B. In the wafer evaluated this time, a large change in the Bparameter is observed at a position almost opposite (180 degrees) to thenotch.

Note that in a case where the wafer S1 was loaded into an exposuresystem, the system stopped frequently. As the exposure system, a stepper(a common name of a stepping projection exposure system) was used inwhich the wafer is repeatedly stepped and exposed to a projected imageof a mask pattern (a reticle pattern). As the exposure system, there maybe used a scanning exposure system. The present inventors have seriouslyinvestigated the abnormal stop of the stepper and conceived that thestop may be greatly influenced by the uniformity in a peripheral portionof the B parameter obtained using the above method for evaluating thewafer configuration.

This is considered because if there is a large change in the B parameter(local sags) in a wafer as shown in FIG. 4, a focus of the exposuresystem is displaced which makes impossible of control by auto-focusing,so that a focus error arises to stop the system abnormally.

Therefore, evaluation was performed on an average value, a standarddeviation, a maximum value, a minimum value and (a maximum value−aminimum value) of plural surface characteristics A, B or (A−B). Resultsof the evaluation are shown in Table 1. While changes (variations) inthe parameter can be visually observed when the graph as shown in FIG. 4is prepared, quantitative evaluation can also be performed by obtaining(the maximum value−the minimum value), the standard deviation andothers. In the present invention, evaluation can be performedquantifying uniformity of the configuration in a peripheral portion ofthe wafer.

TABLE 1 Example 1 Evaluation Results: Uniformity of Configuration inWafer Peripheral Portion (measurement object: wafer S1) Maximum −Standard Maximum Minimum Minimum Average deviation (μm) (μm) (μm) (μm)(μm) A 0.135 −0.029 0.164 0.038 0.028 parameter B −0.183 −0.919 0.736−0.480 0.143 parameter (A − B) 0.942 0.223 0.719 0.518 0.141 parameter

Example 2

In order to confirm the above findings, evaluation was performed onwafers manufactured in plural different wafer manufacturing processes bymeans of the above method for evaluating a wafer configuration. To beconcrete, wafers were manufactured altering wafer manufacturingprocesses so as to decrease a uniformity value of a peripheral portionin the B parameter.

Generally, the wafer manufacturing process comprises, a slicing step ofslicing the single crystal ingot with a wire saw or the like to obtain athin and disk-shaped wafer; a chamfering step of chamfering a peripheraledge portion of the wafer obtained through the slicing step to preventcracking and chipping of the wafer; a lapping step of flattening thiswafer; a flattening step of surface grinding or the like; an etchingstep that removes machining deformation remaining behind in the sochamfered and flattened wafer; a polishing step of making a mirrorsurface of the wafer; and a cleaning step of cleaning the polished waferto remove an abrasive slurry or dust particles deposited thereon.

Various methods are conceived as the above steps in the manufacturingprocess to improve uniformity of the peripheral portion in the Bparameter. For example, as an improvement in the slicing step, it is notto make irregular cut-in in the peripheral portion of the wafer by awire when using a wire saw and the like. It is also to slice the waferso as to improve a wafer configuration such as a bow and a sori. For thepurpose, there are methods for controlling a slurry temperature, a feedrate of a wire and others.

As an improvement in the chamfering step, it is to perform grinding andmirror-chamfering while taking care of uniformity in chamfering. Forthis end, it is to perform the chamfering so as to control uniformly acontact pressure of a grindstone, a buff or the like. It is also tocontrol it with the number of rotation of the wafer and the grindstone(buff) or the like.

As an improvement in the etching step, it is to take care of uniformityof etching. Especially, the etching is performed controlling uniformlystreams of the etchant. For this end, there is a method to control thespeed of rotation of an etching drum and others. It is also to improveit by reducing a contact area between the etching drum supporting wafersand the wafers.

As an improvement in the surface grinding step or the lapping step, itis to machine the wafer controlling spark-out because work damages andthe like are easily generated when a fixed grindstone or a lapping tableare sparked out after the lapping is over. In the surface grinding,adjustment is made on a grain size of the grindstone, a rotation speedthereof, a feed speed thereof so as to generate grinding striations atthe lowest level possible. There are also available a method to removethe grinding striations by adopting low damage lapping and othermethods.

As improvements in the polishing step, there are following measures:adjustments of a polishing pressure applied on a peripheral portion of awafer in polishing, that is a change in a size of a work holding plate,polishing such that the central portion of a work holding region is of aharder quality while a peripheral portion thereof is of a softer qualityand the peripheral portion is vacuum-chucked; and a back surface coat isformed on a back surface of a work, the work is held via the backsurface coat and a front surface of the work is polished, whereinthickness of the back surface coat is different between the peripheralportion and the central portion in polishing. By changing a polishingpressure on the peripheral portion with the above methods, peripheralsags can be controlled. There is also usable a polishing method in whicha pushing pressure applied on a work peripheral portion is controlledindependently of the central portion by changing a polishing head.

In this example, the above improving methods are combined mainly with aprocess including a slicing step; a chamfering step; a surface grindingstep; an etching step; a low damage lapping step; and a polishing stepto obtain wafers S2, S3 and S4 manufactured by three different wafermanufacturing processes.

The wafers were evaluated according to the method for evaluating a waferconfiguration of the present invention to obtain graphs of FIG. 5 (waferS2), FIG. 6 (wafer S3) and FIG. 7 (wafer S4) in respect of the abovethree processes. A wafer configuration evaluation method is the same asin Example 1.

Moreover, quantitative evaluation was performed on the average value,the standard deviation, the maximum value, the minimum value, and (themaximum value−the minimum value) of the surface characteristic A, thesurface characteristic B or the surface characteristic (A−B) of eachwafer. Results of the evaluation are shown in Tables 2 to 4. The abovewafers were loaded into a stepper, no abnormal stop of the apparatusbeing observed. As to the wafers, as can be seen from Table 3, adifference between the maximum value and the minimum value of pluralsurface characteristics B (peripheral portion uniformity in the Bparameter) obtained on each wafer was 600 nm or less, that is 556 nm,390 nm and 486 nm, respectively. Furthermore, as can be seen from Table4, uniformity of a peripheral portion in the surface characteristic(A−B) was 500 nm or less, that is 419 nm, 404 nm and 380 nm. Thesewafers S2, S3 and S4 were good in a process using a stepper.

TABLE 2 A Parameter Peripheral Portion Uniformity Maximum − StandardMaximum Minimum Minimum Average deviation (μm) (μm) (μm) (μm) (μm) WaferS2 0.330 −0.007 0.337 0.110 0.079 (Example 2) Wafer S3 0.241 −0.0240.265 0.104 0.055 (Example 2) Wafer S4 0.253 −0.020 0.272 0.093 0.060(Example 2) Wafer S5 0.105 −0.028 0.132 0.032 0.024 (Com- parativeExample 1) Wafer S1 0.135 −0.029 0.164 0.038 0.028

TABLE 3 B Parameter Peripheral Portion Uniformity Maximum − StandardMaximum Minimum Minimum Average deviation (μm) (μm) (μm) (μm) (μm) WaferS2 0.002 −0.553 0.556 −0.309 0.111 (Example 2) Wafer S3 −0.124 −0.5150.390 −0.300 0.073 (Example 2) Wafer S4 −0.008 −0.494 0.486 −0.288 0.100(Example 2) Wafer S5 −0.253 −0.935 0.682 −0.509 0.154 (Com- parativeExample 1) Wafer S1 −0.183 −0.919 0.736 −0.480 0.143

TABLE 4 (A − B) Parameter Peripheral Portion Uniformity Maximum −Standard Maximum Minimum Minimum Average deviation (μm) (μm) (μm) (μm)(μm) Wafer S2 0.636 0.251 0.384 0.419 0.074 (Example 2) Wafer S3 0.6190.215 0.404 0.404 0.069 (Example 2) Wafer S4 0.579 0.195 0.385 0.3800.070 (Example 2) Wafer S5 0.930 0.282 0.648 0.541 0.157 (Com- parativeExample 1) Wafer S1 0.942 0.223 0.719 0.518 0.141

Comparative Example 1

Then, evaluation was performed on a wafer manufactured in a common wafermanufacturing process as Comparative Example 1. The wafer manufacturingprocess comprises, a slicing step of slicing the single crystal ingot toobtain a thin and disk shaped wafer; a chamfering step of chamfering aperipheral edge portion of the wafer obtained through the slicing stepto prevent cracking and chipping of the wafer; a lapping step offlattening this wafer; an etching step that removes machiningdeformation remaining behind in the so chamfered and lapped wafer; apolishing step of making a mirror surface of the wafer; and a cleaningstep of cleaning the polished wafer to remove an abrasive slurry or dustparticles deposited thereon. The wafer manufactured from the commonwafer manufacturing process was referred to as S5.

Evaluation was performed on the wafer S5 according to the method forevaluating a wafer configuration of the present invention so as toobtain a graph as shown in FIG. 8. Furthermore, quantified evaluationresults are additionally shown in Tables 2 to 4. A configurationevaluation method is the same as Example 1.

The wafer S5 was loaded into a stepper with the result that abnormalstop of the stepper was observed at a rate of 100%. A difference betweenthe maximum value and the minimum value (the B parameter peripheralportion uniformity) of plural surface characteristics B obtained on awafer was 682 nm. Uniformity of a peripheral portion in the surfacecharacteristic (A−B) was 648 nm. Evaluation results of the wafer S1evaluated in Example 1 are also additionally shown in Tables 2 to 4.Abnormal stop of the stepper was also observed with the wafer S1. Thus,the wafers S1 and S5 were poor in a process using the stepper. It isfound that a local change in the B parameter exerts a large influence onstop of the apparatus.

As for wafers S1 to S5, there are shown the peripheral portionuniformity (the maximum value−the minimum value) in the B parameter inFIG. 9 and the peripheral portion uniformity (the maximum value−theminimum value) in the (A−B) parameter in FIG. 10. It is found that awafer with the B parameter peripheral portion uniformity of 600 nm orless is good and a wafer with the (A−B) parameter peripheral portionuniformity of 500 nm or less is good.

Example 3

Even in the wafer manufacturing process shown in Example 2, the Bparameter uniformity was not able to be reduced to be perfectly 600 nmor less. Accordingly, wafers were evaluated according to theconfiguration evaluation method of the present invention to sortedwafers within the scope of the present invention and thereafter, thesorted wafers were loaded into a device process. To be concrete, wafershaving the surface characteristic B peripheral portion uniformity of 600nm or less (these wafers had the surface characteristic (A−B) peripheralportion uniformity of 400 nm or less) were loaded into a stepper processand operations of the stepper were observed. As a result, it wasconfirmed that the stepper was not stopped at all.

Comparative Example 2

Wafers manufactured in a common wafer manufacturing process were loadedinto a stepper process without sorting of the wafers. As a result,abnormal stop of the stepper was observed. Stop of the apparatusoccurred at a frequency of the order of 10% of processed wafers.Evaluation on a wafer causing abnormality according to the presentinvention shows that the wafer peripheral portion uniformity in thesurface characteristic B was 600 nm or more. Moreover, the waferperipheral portion uniformity in the surface characteristic (A−B) (themaximum value−the minimum value) was also 600 nm or more. Note thatabnormal stop occurred or did not occur for wafers having the peripheralportion uniformity in the surface characteristic B of the order in therange of 500 nm to 700 nm. When this value is 600 nm or less, anoccurrence frequency of the apparatus stop is greatly reduced, whereasthere was a case where preferable wafers were not sorted precisely withthe B parameter alone. By evaluating wafers with the peripheral portionuniformity in the surface characteristic (A−B), the wafers arecontrolled more precisely. Especially, wafers with this value of theorder of 400 nm or less cause no abnormal stop.

There is a case where abnormal stop does not occur for a wafer havingthe peripheral portion uniformity in the B parameter of 600 nm or moreand therefore, while it is not necessarily conceived that the cause forstop of a stepper is limited to the above factors, it may be conceivedin view of the above matter that the factors evaluated in the presentinvention exert a large influence thereon.

That is to say, in the stepper process, the peripheral portionuniformity in the B parameter is especially important and it is foundthat abnormal stop of the apparatus is reduced using wafers with (themaximum value−the minimum value) of 600 nm or less among the peripheralportion configuration uniformity. Using wafers with (the maximumvalue−the minimum value) in the (A−B) parameter uniformity of 400 nm orless, stop of the apparatus is greatly reduced, resulting in improvementon a product yield as well.

Furthermore, in evaluation of the peripheral portion uniformity, stableevaluation was ensured when an arbitrary position X of the evaluationmethod of the present invention is set at a position of 30 mm from thewafer peripheral portion and measurement of the wafer configuration isperformed using date obtained from an area excluding 1 mm of the waferperiphery (excluding a chamfered portion).

CAPABILITY OF EXPLOITATION IN INDUSTRY

Typical effects of the present invention will be described below.Displacement or a thickness measured with a prescribed space using adisplacement or thickness measuring means can define a waferconfiguration more precisely by using a surface characteristiccalculating means than a conventional index indicating flatness such asSFQR. Especially, since the peripheral portion uniformity in the Bparameter can be quantitatively evaluated, it can be determined surelywhether a wafer is good or poor on a prescribed criterion.

In the configuration evaluation method of the present invention, qualitythat has not been precisely evaluated until now, especially quality of aperipheral portion configuration of a wafer can be quantitativelyevaluated, and thereby a wafer configuration most suitable forlithography can be defined.

By defining wafers with values of peripheral portion uniformity in the Bparameter and the (A−B) parameter (the maximum value−the minimum valueof evaluated values), preferable wafers for a device process can besorted.

By using the surface characteristic obtained according to the waferconfiguration evaluation method of the present invention, evaluation canbe more precisely than conventional wafer configuration evaluation andhence abnormality in a device process is prevented, resulting inimprovement on a product yield.

1. A method for evaluating a wafer configuration comprising the stepsof: obtaining plural wafer configuration profiles of from the centralportion of a wafer to the edge portion thereof along the entireperiphery thereof at a prescribed angular space; providing a firstregion for calculating a reference line for each of the profiles in thecentral side of the wafer; calculating the reference line in the firstregion; further providing a second region in the peripheral side of thewafer outside the first region; extrapolating the reference linecalculated in the first region to the second region; analyzing a value(an actually measured value−a reference value) obtained by subtractingthe reference line (the reference value) in the second region from aconfiguration (the actually measured value) in the second region;calculating the maximum value among the values as a surfacecharacteristic A and the minimum value among the values as a surfacecharacteristic B; and evaluating configuration uniformity in theperipheral portion of the wafer from plural surface characteristics Aand surface characteristics B obtained along the entire peripheralportion of the wafer.
 2. The method for evaluating a wafer configurationaccording to claim 1, wherein the configuration uniformity in theperipheral portion of the wafer is evaluated from a difference betweenthe maximum value and the minimum value of the plural surfacecharacteristics A obtained in the peripheral portion of the wafer. 3.The method for evaluating a wafer configuration according to claim 1,wherein the configuration uniformity in the peripheral portion of thewafer is evaluated from a difference between the maximum value and theminimum value of the plural surface characteristics B obtained in theperipheral portion of the wafer.
 4. The method for evaluating a waferconfiguration according to claim 1, wherein a difference (a surfacecharacteristic (A−B)) between the surface characteristic A and thesurface characteristic B is obtained from each of the profiles, and theconfiguration uniformity in the peripheral portion of the wafer isevaluated from a difference between the maximum value and the minimumvalue of the plural surface characteristics (A−B) obtained in theperipheral portion of the wafer.
 5. The method for evaluation a waferconfiguration according to claim 1, wherein the configuration uniformityin the peripheral portion of the wafer is evaluated with standarddeviations of plural surface characteristics A, surface characteristicsB or differences therebetween (surface characteristics (A−B)) obtainedin the peripheral portion of the wafer.
 6. The method for evaluating awafer configuration according to claim 1, wherein the waferconfiguration profile is a value measured with a prescribed space withina surface of the wafer, and displacement in the direction vertical tothe wafer surface or a thickness of the wafer.
 7. The method forevaluating a wafer configuration according to claim 6, wherein theprescribed space for measurement is 1 mm or less.
 8. The method forevaluating a wafer configuration according to claim 1, wherein theprescribed angular space to obtain the wafer configuration profiles is 1degree or less.
 9. A wafer evaluated by the method for evaluating awafer configuration according to claim 1, wherein a difference betweenthe maximum value and the minimum value of plural surfacecharacteristics B obtained within a surface of the wafer (the Bparameter peripheral portion uniformity) is 600 nm or less.
 10. A waferevaluated by the method for evaluating a wafer configuration accordingto claim 1, wherein a difference between the maximum value and theminimum value of plural surface characteristics (A−B) obtained within asurface of the wafer (the (A−B) parameter peripheral portion uniformity)is 500 nm or less.
 11. The wafer according to claim 10, wherein adifference between the maximum value and the minimum value of pluralsurface characteristics (A−B) obtained within the wafer surface (the(A−B) parameter peripheral portion uniformity) is 400 nm or less.
 12. Awafer sorting method, wherein there are sorted wafers each having adifference between the maximum value and the minimum value of pluralsurface characteristics B (the B parameter peripheral portionuniformity) of 600 nm or less evaluated by the method for evaluating awafer configuration according to claim 1, the sorted wafers being usedin an exposure system.
 13. A wafer sorting method, wherein there aresorted wafers each having a difference between the maximum value and theminimum value of plural surface characteristics (A−B) (the (A−B)parameter peripheral portion uniformity) of 500 nm or less evaluated bythe method for evaluating a wafer configuration according to claim 1,the sorted wafers being used in an exposure system.
 14. The wafersorting method according to claim 13, wherein there are sorted waferseach having a difference between the maximum value and the minimum valueof plural surface characteristics (A−B) (the (A−B) parameter peripheralportion uniformity) of 400 nm or less.